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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci? cations without notice. december 2005 rev. 1 wv3eg216m64stsu-d4 256mb C 2x16mx64 ddr sdram unbuffered description the wv3eg216m64stsu is a 2x16mx64 double data rate sdram memory module based on 256mb ddr sdram components. the module consists of eight 16mx16 ddr sdrams in 66 pin tsop package mounted on a 200 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * this product is under development, is not quali? ed or characterized and is subject to change without notice. features double-data-rate architecture pc2700@cl=2.5 bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2,5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh, (8k/64ms refresh) serial presence detect with eeprom power supply: v cc /v ccq : 2.5v 0.20v dual rank standard 200 pin so-dimm package ? package height options: d4: 31.75mm (1.25") note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option operating frequencies ddr333@cl=2.5 clock speed 166mhz cl-t rcd -t rp 2.5-3-3
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 pin names a0 C a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs7 data strobe input/output ck0, ck1 clock input ck0#, ck1# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable dm0-dm7 data-in mask v cc power supply v ccq power supply for dqs v ss ground v ref power supply for reference v ccspd serial eeprom power supply sda serial data i/o scl serial clock sa0-sa2 address in eeprom nc no connect pin configurations pin symbol pin symbol pin symbol pin symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7 dq1 57 v cc 107 a5 157 v cc 8 dq5 58 v cc 108 a4 158 ck1# 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 ck1 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 nc 121 cs0# 171 dq50 22 v cc 72 nc 122 cs1# 172 dq54 23 dq9 73 nc 123 nc 173 v ss 24 dq13 74 nc 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 nc 127 dq32 177 dq56 28 v ss 78 nc 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v cc 30 dq14 80 nc 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 nc 133 dqs4 183 dqs7 34 v cc 84 nc 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 functional block diagram cs1# cs0# dqs0 dm0 dqs1 dm1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 cs# cs# ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dqs4 dm4 dqs5 dm5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 cs# cs# ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dqs2 dm2 dqs3 dm3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 cs# cs# ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dqs6 dm6 dqs7 dm7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 cs# cs# ldqs ldm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 udqs udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 ba0, ba1 a0-a12 ras# ba0, ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams we#: ddr sdrams cas# cke0 we# cke1: ddr sdrams cke1 ddr sdram ddr sdram v ccspd v cc /v ccq v ref v ss ddr sdram spd a0 sa0 serial pd sda a1 sa1 a2 sa2 wp scl *clock net wiring card edge ddr sdrams ddr sdrams ddr sdrams ddr sdrams r = 120 ohm ck0/1/2 ck0/1/2# clock wiring clock input sdrams 4 sdrams 4 sdrams nc ck0/ck0# ck1/ck1# ck2/ck2# notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs# relationships must be maintained as shown. note: all resistor values are 22 ohms unless otherwise speci? ed.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v cc and v ccq supply relative to v ss v cc, v ccq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c operating temperature t a 0 ~ 70 c power dissipation p d 8w short circuit output current i os 50 ma notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70c, v cc = 2.5v 0.2v parameter symbol min max unit note supply voltage ddr266/ddr333 (nominal v cc of 2.5v) v cc 2.3 2.7 i/o supply voltage ddr266/ddr333 (nominal v cc of 2.5v) v ccq 2.3 2.7 v i/o reference voltage v ref 0.49*v ccq 0.51*v ccq v1 i/o termination voltage v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ccq +0.30 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck# v in (dc) -0.3 v ccq +0.30 v input differential voltage, ck and ck# v id (dc) 0.3 v ccq +0.60 v 3 input crossing point voltage, ck and ck# v ix (dc) 0.3 v ccq +0.60 v input leakage current addr, cas#, ras#, we# i i -16 16 ua cs#, cke -8 8 ua ck, ck# -8 8 ua dm -4 4 ua output leakage current i oz -10 10 ua output high current (normal strengh); v out = v +0.84v i oh -16.8 ma output high current (normal strengh); v out = v tt -0.84v i ol 16.8 ma output high current (half strengh); v out = v tt +0.45v i oh -9 ma output high current (half strengh); v out = v tt -0.45v i ol 9ma notes: 1. v ref is expected to be equal to 0.5*v ccq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed 2% of the dc value 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors,is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck#. capacitance v cc = 2.5v, v ccq =2.5v, t a = 25c, f = 1mhz parameter symbol min max unit input capacitance (a0-a12, ba0-ba1, ras#, cas#, we#) c in1 20 28 pf input capacitance (cke0, cke1) c in2 12 16 pf input capacitance (cs0#, cs1#) c in3 12 16 pf input capacitance (ck0,ck0#, ck1, ck1#) c in4 12 16 pf input capacitance (dm0-dm7) c in5 12 14 pf data and dqs input/output capacitance (dq0-dq63), cb0-7 c out 12 14 pf
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 ac operating test conditions parameter/condition symbol min max unit note input high (logic 1) voltage v ih(ac) v ref +0.31 v 1 input low (logic 0) voltage v il(ac) v ref -0.31 v 1 input differential voltage, ck and ck# inputs v id(ac) 0.7 v ccq +0.6 v input crossing point voltage, ck and ck# inputs v ix(ac) 0.5*v ccq -0.2 0.5*v ccq +0.2 v notes: 1. v ih overshoot: v ih = v ccq +1.5v for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. v il undershoot: v il = -1.5v for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 i dd specifications and test conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol conditions ddr333 @ cl = 2.5 max unit operating current - one bank active- precharge i dd0* t rc = t rc (min); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 372 ma operating current - one bank operation i dd1* one bank open, bl=4, reads - refer to the following page for detailed test condition 512 ma percharge power- down standby current i dd2p** all banks idle; power - down mode; cke = = v ih (min);all banks idle; cke > = v ih (min); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; address and other control inputs changing once per clock cycle; v in = v ref for dq,dqs and dm 240 ma active power - down standby current i dd3p** one bank active; power-down mode; cke=< v il (max); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; v in = v ref for dq, dqs and dm 280 ma active standby current i dd3n** cs# > = v ih (min); cke> = v ih (min); one bank active; active - precharge; t rc = t ras max; t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 440 ma operating current - burst read i dd4r* burst length = 2; reads; continguous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2 at t ck = 100mhz for ddr200, cl = 2 at t ck = 133mhz for ddr266a, cl = 2.5 at t ck = 133mhz for ddr266b ; 50% of data changing at every burst; lout = 0ma 812 ma operating current - burst write i dd4w* burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; cl = 2 at t ck = 100mhz for ddr200, cl = 2 at t ck = 133mhz for ddr266a, cl = 2.5 at t ck = 133mhz for ddr266b ; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst 772 ma auto refresh current i dd5** t rc = t rfc (min) - 8*t ck for ddr200 at 100mhz, 10*t ck for ddr266a & ddr266b at 133mhz; distributed refresh 1440 ma self refresh current; cke =< 0.2v i dd6** external clock should be on; t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b 24 ma orerating current - four bank operation i dd7a* four bank interleaving with bl=4 -refer to the following page for detailed test condition 1412 ma note: i dd speci? cation is based on samsung components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operation condition and other module rank in i dd2p (cke low) mode. ** value calculated as all module ranks in this operation condition.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 i dd specifications and test conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol conditions ddr333 @ cl = 2.5 max unit operating current - one bank active- precharge i dd0* t rc = t rc (min); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 288 ma operating current - one bank operation i dd1* one bank open, bl=4, reads - refer to the following page for detailed test condition 304 ma percharge power- down standby current i dd2p** all banks idle; power - down mode; cke = = v ih (min);all banks idle; cke > = v ih (min); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; address and other control inputs changing once per clock cycle; v in = v ref for dq,dqs and dm 200 ma active power - down standby current i dd3p** one bank active; power-down mode; cke=< v il (max); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; v in = v ref for dq, dqs and dm 80 ma active standby current i dd3n** cs# > = v ih (min); cke> = v ih (min); one bank active; active - precharge; t rc = t ras max; t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 312 ma operating current - burst read i dd4r* burst length = 2; reads; continguous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2 at t ck = 100mhz for ddr200, cl = 2 at t ck = 133mhz for ddr266a, cl = 2.5 at t ck = 133mhz for ddr266b ; 50% of data changing at every burst; lout = 0ma 364 ma operating current - burst write i dd4w* burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; cl = 2 at t ck = 100mhz for ddr200, cl = 2 at t ck = 133mhz for ddr266a, cl = 2.5 at t ck = 133mhz for ddr266b ; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst 408 ma auto refresh current i dd5** t rc = t rfc (min) - 8*t ck for ddr200 at 100mhz, 10*t ck for ddr266a & ddr266b at 133mhz; distributed refresh 944 ma self refresh current; cke =< 0.2v i dd6** external clock should be on; t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b 16 ma orerating current - four bank operation i dd7a* four bank interleaving with bl=4 -refer to the following page for detailed test condition 844 ma note: i dd speci? cation is based on nanya components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operation condition and other module rank in i dd2p (cke low) mode. ** value calculated as all module ranks in this operation condition.
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs december 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 ddr sdram component electrical characteristics and recommended ac operating conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol 335 unit min max row cycle time t rc 60 ns refresh row cycle time t rfc 72 ns row active t ras 42 120k ns ras# to cas# delay t rcd 18 ns row precharge time t rp 18 ns row active to row active delay t rrd 12 ns write recovery time t wr 15 ns last data into read command t wtr 1t ck clock cycle time cl=2.5 t ck 612ns clock high level width t ch 0.45 0.55 t ck clock low level width t cl 0.55 0.55 t ck dqs-out access time from ck/ck# t dqsck -0.6 +0.6 ns output data access time from ck/ck# t ac -0.7 +0.7 ns data strobe edge to output data edge t dqsq - 0.45 ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.4 0.6 t ck ck to valid dqs-in t dqss 0.75 1.25 t ck dqs-in setup time t wpres 0ns dqs-in hold time t wpre 0.25 t ck dqs falling edge to ck rising-setup time t dss 0.2 t ck dqs falling edge to ck rising-hold time t dsh 0.2 t ck dqs-in high level width t dqsh 0.35 t ck dqs-in low level width t dqsl 0.35 t ck address and control input setup time (fast) t is 0.75 ns address and control input hold time (fast) t ih 0.75 ns address and control input setup (slow) t is 0.7 ns address and control input hold time (slow) t ih 0.7 ns data-out high impedence time from ck/ck# t hz -0.7 +0.7 ns data-out low impedence time from ck/ck# t lz -0.7 +0.7 ns mode register set cycle time t mrd 10 ns dq & dm setup time to dqs t ds 0.4 ns dq & dm hold time to dqs t dh 0.4 ns control & address input pulse width t ipw 2.2 ns dq & dm input pulse width t dipw 1.75 ns exit self refresh o non-read command t xsnr 75 ns exit self refresh to read command t xsrd 200 t ck refresh interval time t refi 7.8 us output dqs valid window t qh t hp - t qhs ns clock half period t hp t cl min or t ch min ns data hold skew factor t qhs 0.55 ns dqs write postamble t wpst 0.4 0.6 ns active read with auto precharge command t rap 18 ns auto precharge write recovery + precharge time t ral (t wr /t ck ) + (t rp /t ck )t ck
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs december 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 * all dimensions are in millimeters and (inches) 67.60 (2.661) 63.60 (2.504) 1.0 0.1 (0.04 0.0039) 3.80 (0.150) max. 2.15 (0.085) 6.0 0.236 4.20 (0.165) 1.8 (0.071) 4.00 (0.158) min. 47.40 (1.866) 2- 1.80 (0.071) 11.40 (0.449) 13941 199 31.75 (1.25) full r 2x 2.40 (0.094) 4.00 0.10 (0.158 0.039) 20 (0.787) 2.45 (0.098) 4.00 0.10 (0.158 0.039) 1.00 0.1 (0.04 0.0039) 0.45 0.03 (0.018 0.001) 0.60 (0.024) 2.55 min (0.102 min) 0.25 (0.01) package dimensions for d4 ordering information for d4 part number speed height* wv3eg216m64stsu335d4xg 166mhz/333mbps, cl=2.5 31.75mm (1.25") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung, n = nan ya & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option tolerances: 0.15 (0.006) unless otherwise speci? ed
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs december 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 part numbering guide wv 3 e g 216m 64 s t s u xxx d4 x g wedc memory ddr gold depth (daul rank) bus width x16 tsop 2.5v unbuffered speed (mhz) package 200 pin component vendor name (m = micron) (s = samsung) (n = nanya) g = rohs compliant
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs december 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* wv3eg216m64stsu-d4 document title 256mb C 2x16mx64, ddr sdram unbuffered revision history rev # history release date status rev 0 created 8-05 preliminary rev 1 1.1 added samsung i dd specs 12-05 preliminary

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